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۱A Complete Study on Theoretical Representation of Harmonic Distortion in Balanced Pseudo Differential OTA
نویسنده(ها): ، ،
اطلاعات انتشار: شانزدهیمن کنفرانس مهندسی برق ایران، سال
تعداد صفحات: ۵
High frequency harmonic distortion of CMOS balanced pseudo differential operational transconductance amplifier (PD OTA) is analyzed in this paper with the aim to reduce the effects of harmonic distortion into a simple equation. The analysis consists of a theoretical study using Volterra series and simulation results using HSPICE. Analysis and simulations results clear that the mechanism of harmonic distortion in balanced PD OTA is complex but can be represented by simple equation in low and high frequency. Frequency–dependent harmonic distortion reveals effects of memorized component of balanced PD OTA in linearity decreasing versus frequency increasing. Influences of current mirror’s nonlinearity, circuit’s parameters, parasitic capacitances and load’s impedance are considered.<\div>

۲Boost PFC Converters with Integral and Double Integral Sliding Mode Control
نویسنده(ها): ، ،
اطلاعات انتشار: نوزدهمین کنفرانس مهندسی برق ایران، سال
تعداد صفحات: ۶
In this article, sliding mode controller is used to improve power factor in AC–DC boost converters. A comparison between integral sliding mode controller (ISMC) and double integral sliding mode controller (DISMC) for the current loop of the boost PFC converter is proposed in this paper. In sliding mode control method, circuit complexity is less. Also good stability and fast response versus to the changes of load, source and parameters of the circuit are obtained. In this paper by using second order Sliding Mode, we reduced chattering. The simulations have been done by MATLAB and simulations shown good performance of the DISMC compared with ISMC against load, source and parameters of the circuit changes. The results are: close to unity power factor, low THD, constant output voltage, low chattering and low steady state error. Also converter performance is shown in high frequency application<\div>

۳A Highly–Linear Modified Pseudo–Differential Current Starved Delay Element with Wide Tuning Range
نویسنده(ها): ، ،
اطلاعات انتشار: نوزدهمین کنفرانس مهندسی برق ایران، سال
تعداد صفحات: ۴
This paper describes an efficient structure of a pseudo–differential current starved delay element that is used in a four stages delay line targeted for analog\mixed Delay– Locked–Loops. The designed circuit has been simulated in ADS software, using TSMC 0.18 um CMOS process at 1.5V supply voltage. Body feed technique is used to widen applicable range of control voltage. The linearity of circuit is, also, improved compared to the conventional current starved delay elements. Moreover, improving the noise performance is achieved by taking advantage of differential structure. The simulation results indicate that tunable delay range of proposed delay cell is within 0.26–1.6 ns. Sweeping the control voltage from 0 to 1.2 V at 350 MHz, the calculated gain is almost 1.11ns\V. The operation frequency range of the four stages delay line is 180 to 500 MHz. While operating at 350 MHz, the peak–to–peak and rms jitters are 9.5 and 32 ps, respectively, and the maximum power consumption in this frequency is 0.4 mW.<\div>

۴A Fast Lock Time Pulsewidth Control Loop using Second Order Passive Loop Filters
نویسنده(ها): ،
اطلاعات انتشار: نوزدهمین کنفرانس مهندسی برق ایران، سال
تعداد صفحات: ۵
This paper presents a usage of the second order loop filters for PWCLs. The analysis shows that by using this kind of loop filters, lock time is much better than conventional PWCLs and is comparable with PWCLs using fast locking circuits. Also, power consumption of the PWCLs using second order filters are less than the fast locking PWCLs. A 0.18m CMOS technology and 1.8V supply voltage are used to verify the operation of the proposed circuit. The simulation results show that the proposed PWCL reduces the lock time to 405ns. The proposed PWCL operates from 400MHz to 1.4GHz. The duty cycle of the input clock is from 10% to 80% and the duty cycle of the output clock is from 30% to 60% in step of 10%. With an input clock operating at 1GHz lock time and power dissipation of the PWCL are 390ns and 0.187mW, respectively<\div>
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