توجه: محتویات این صفحه به صورت خودکار پردازش شده و مقاله‌های نویسندگانی با تشابه اسمی، همگی در بخش یکسان نمایش داده می‌شوند.
۱DOUBLE EDGE TRIGGERED MODIFIED HYBRID LATCH FLIPFLOP (DMHLFF)
اطلاعات انتشار: دوازدهیمن کنفرانس مهندسی برق ایران، سال
تعداد صفحات: ۶
In this paper a new low power flip–flop called Double–edge triggered Modified Hybrid Latch Flip–Flop (DMHLFF) has been proposed and compared to previous flip–flops. DMHLFF is a low power, low area, and fast flip–flop. Power consumption is reduced by avoiding unnecessary internal node transition. Power consumption in clock tree is also reduced by decreasing the frequency of clock to half f the cock frequency in single edge triggered flipflop for the same throughput. These capabilities are obtained by modifying the structure of conventional Hybrid Latch Flip–Flop without any penalty in area. Reducing the number of transistor in stack leads to having less delay and thus higher operational speed compared to others flip–flops<\div>

۲A NEW TEST PATTERN GENERATEOR BY ALTERING THE STRUCTURE OF 2–D LFSR FOR BUILT IN SELF TEST APPLICATION
اطلاعات انتشار: دوازدهیمن کنفرانس مهندسی برق ایران، سال
تعداد صفحات: ۶
In this paper a ROM–less deterministic test pattern generator (TPG) has been proposed for test per clock scheme. This TPG consists of a two dimensional linear feedback shift register (2–D LFSR) and a controller. The controller configures the structure of 2–D LFSR and it has a quite simple structure and a very low area overhead. Simulated annealing algorithm is used to find the coefficient matrix of 2–D LFSR. Test application time and power consumption is significantly reduced using this technique while keeping fault coverage at 100%. Compared to the previous works, the proposed method is able to generate a much larger set of deterministic test vectors with approximately the same number of flip flops. Experimental results are shown for ISCAS’85 benchmarks.<\div>
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