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۱Clock Delayed Domino Logic with an Efficient Variable Voltage Keeper Threshold
نویسنده(ها): ، ،
اطلاعات انتشار: سیزدهیمن کنفرانس مهندسی برق ایران، سال
تعداد صفحات: ۵
In this work, the domino logic with the variable threshold voltage keeper which uses an efficient body bias is proposed. The generator which consists of a capacitor and a diode is based on the voltage doubler technique. In the proposed scheme, the keeper size may be increased to
improve the noise–immunity of the domino logic without significantly increasing the power and the delay. In addition, the proposed generator circuit is simple, consumes a smaller area, and operates with a single supply voltage. The results of simulation for a 0.18µm CMOS technology
shows an improvement of 18% and 59% in power and delay, respectively, for this technique compared to the standard domino logic.<\div>

۲Design of Merged Differential Cascode Voltage Switch with Pass–Gate (MDCVSPG) Logic for High–Performance Digital Systems
نویسنده(ها): ، ،
اطلاعات انتشار: سیزدهیمن کنفرانس مهندسی برق ایران، سال
تعداد صفحات: ۵
In this paper, a new high performance yet low power circuit technique called merged differential cascode voltage switch with pass– gate (MDCVSPG) is introduced. It combines the benefits of two logic styles of EDCVSL and DCVSPG. To verify the efficiency of the proposed logic, gates NAND, NOR, and XOR for the logic styles are simulated using HSPICE. The results show better performance and lower power onsumption for MDCVSPG compared to EDCVSL and DCVSPG. In addition, when is used in design of an 8 bit ripple carry adder, the proposed style consumes 38% less silicon area compared to DCVSPG. The area efficiency is due to a reduction of transistor number and layout
complexity.<\div>

۳LPPM: Low Power Partitioned Multiplier
نویسنده(ها): ، ، ،
اطلاعات انتشار: سیزدهیمن کنفرانس مهندسی برق ایران، سال
تعداد صفحات: ۵
In this paper, a new architecture for low–power multipliers is proposed. The reduction of the power consumption is achieved through reducing the circuit activity at the architecture level. In the proposed technique, depending on the Hamming distance of the current and previous input operands, either original or two's complement form of the operands are used. The multiplier circuit is divided into partitions of smaller multipliers and the approach is applied to lower partitions (bits) of the operand. To assess the efficiency, the technique is applied to JPEG decoder multiplier for some standard pictures. The results show more than 18% switching activity reduction compared to conventional array multiplier.<\div>
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