توجه: محتویات این صفحه به صورت خودکار پردازش شده و مقاله‌های نویسندگانی با تشابه اسمی، همگی در بخش یکسان نمایش داده می‌شوند.
۱A Stable Weighted Clustering Algorithm for Mobile Ad Hoc Networks with Power Saving
اطلاعات انتشار: سومین کنفرانس بین المللی فناوری اطلاعات و دانش، سال
تعداد صفحات: ۶
This paper proposes a new weight based clustering algorithm for mobile ad hoc networks (MANETs). The proposed algorithm takes into account the transmission power, battery power, Tnb (connection duration with neighbors), Dnb (Average of distance with neighbors in Tnb), and the degree of a node for forming clusters. New Parameters of Tnb and Dnb are adopted as two metric to elect CH, in this paper. Using the first parameter increases the stability of cluster architecture. Using the second parameter causes the CHs to consume less power for communication with their neighbors. In this paper, these two parameters are defined and then a mathematical method is presented for their computation. Through simulations we have compared the performance of our algorithm with that of the Lowest–ID, Highest Degree (HD) and WCA algorithms in terms of number of reaffiliations, and power consumed in total network. Results obtained from simulations proved that the proposed algorithm achieves the goals.<\div>

۲The Reduction of Thermal Energy on the 3–Dimensional NOC byProviding an Efficient Mapping Based on Beehive Structure
نویسنده(ها): ،
اطلاعات انتشار: کنفرانس بین المللی مهندسی و علوم کاربردی، سال
تعداد صفحات: ۷
The concept of ‘Network on Chip’ includes processing elements each of which is placed together with a specific functionality in a substructure communication based on their applications. In the world of the systems on the chips, the main goal of the network on chip isto present a solution for simultaneous access to the performance, development and flexibility. Topology, mapping, routing algorithms, power, throughput, latency and performance overhead area and the complexity of connections are among the things that are taken intoconsideration while designing systems on chips. In order to optimize power consumption and delay, the researchers tried to change each of the properties of the network on chip. Although different and optimal mapping methods have been proposed so far and achieved good results in reducing latency and power consumption, but substructures we face the problems of power and temperature control in designing the three–dimensional. In this study, a communicational substructure based on three–dimensional structure of the regular six–sided architecture similar to a beehive is presented, which is improved with an efficient mapping based on spiralmapping. This presentation has been able to optimize the features of a network on chip and has managed a solution to reduce communication cost and power consumption and as a resultdiminishes the average energy consumption across the network.<\div>

۳A Novel Scheme for Fault–Tolerant And Higher Capacity Network on Chip
اطلاعات انتشار: International Journal Information and Communication Technology Research، دوم،شماره۱، may ۲۰۱۰، سال
تعداد صفحات: ۸
As CMOS technology scales down, NoC (Network on Chip) gradually becomes the mainstream of on–chip communication. In this paper we present a methodology to design fault–tolerant routing algorithms for regular direct interconnection networks. It supports fully adaptive routing, does not degrade performance in the absence of faults, and supports a reasonably large number of faults without significantly degrading performance. Consequently, this work examines fault tolerant communication algorithms for use in the Communication Networks including NoC domain. Before two different flooding algorithms, a random walk algorithm and an Intermediate Node Algorithm have been investigated. The first three algorithms have an exceedingly high communication overhead and cause huge congestion in usual traffics. The fourth one which is Intermediate Node algorithm is a static fault–tolerant algorithm which focuses on the faults knowing in advance where they are located. We have developed a new dynamic algorithm based on intermediate node concept and stress value concept to overcome all of blind sides of mentioned algorithms. We have designed a switch\router base on this algorithm and simulated by MAX PLUS II tool and verified it on a mesh NoC in Xilinx environment.
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