توجه: محتویات این صفحه به صورت خودکار پردازش شده و مقاله‌های نویسندگانی با تشابه اسمی، همگی در بخش یکسان نمایش داده می‌شوند.
۱Effect of Don’t Cares on SoC’s Testability and Power
اطلاعات انتشار: هشتمین کنفرانس سالانه انجمن کامپیوتر ایران، سال
تعداد صفحات: ۸
This work explores the relationship between controller synthesis and the testability and power consumption of systems consisting of interacting controllers and datapaths. A novel specification of “don’t cares” in controller synthesis is used, and the impact of the controller state encoding is considered. Results are reported for three different controller synthesis methods.<\div>

۲Double–Edge triggered Level Converter Flip–Flop with Feedback
نویسنده(ها): ،
اطلاعات انتشار: نهمین کنفرانس دانشجویی مهندسی برق، سال
تعداد صفحات: ۵
In this paper, a double–edge triggered level converter flip–flop (DE–LCFFF) is proposed. The flipflop makes use of the conditional discharging technique which effectively suppress the dynamic power consumption during transition time and the selfprecharging technique to automatically precharge its dynamic node after enough time. An explicit doubleedge pulse generator is used to further decrease the power consumption in the proposed LCFF. In addition, the use of pass gate transistors and more simplified structure in the main block of DE–LCFFF leads to a less
leakage power consumption. The increase in the speed is achieved by reducing the number of the stack transistors in the discharge path and using less complicated circuit structure. When compared to the previous level converter flip–flops, the proposed LCFF shows considerable reductions in the power consumption, the delay, and the area.<\div>

۳WAVELET BASED DYNAMIC POWER MANAGEMENT FOR NONSTATIONARY SERVICE REQUESTS
اطلاعات انتشار: دوازدهیمن کنفرانس مهندسی برق ایران، سال
تعداد صفحات: ۶
The goal of dynamic power management is to reduce power dissipation in system level by putting system components into different states. This paper proposes a wavelet based approach that models the device behavior precisely. In spite of conventional stochastic models, this method eliminates some impractical assumptions which were shortcoming for previous methods. The stationary behavior of
devices and the use of a memoryless distribution for device modeling are some of the aforementioned assumptions that have been
relaxed in our model. Additionally, wavelet model can capture the local information accurately. Furthermore this algorithm is adaptive. This method has two additional benefits; firstly according to the device application a suitable wavelet basis can be used. Secondly, it has a sparse time–scale representation indicating that only a few coefficients in their wavelet representation have to be estimated. The simulation results show 95% accuracy in desktop Hard Disk Drive (HDD) states prediction and power saving by a factor of 2.<\div>

۴DELAY AND POWER ESTIMATION OF CMOS INVERTERS
اطلاعات انتشار: یازدهمین کنفرانس مهندسی برق، سال
تعداد صفحات: ۷
In this paper, a new simple yet accurate model for determining the delay and the power consumption of a state of the art static CMOS inverter is introduced. This analytical model uses the modified version of n–th power law MOSFET model which is appropriate for short channel devices. The short–circuit current, which is used in the calculation of the power consumption, is modeled by a piecewise linear interpolation scheme. The short–circuit current used for the interpolation is obtained from the HSPICE simulation with complete level 49 model parameters including all capacitances. For the evaluation of the inverter delay, an accurate model is presented. Although the proposed model is much simpler compared to the previously reported models, it has a very good accuracy which is confirmed with HSPICE simulations<\div>

۵Reducing CMOS Gates to Equivalent Inverters Based on Modified n–th Power Law MOSFET Model
اطلاعات انتشار: یازدهمین کنفرانس مهندسی برق، سال
تعداد صفحات: ۶
A method for modeling a CMOS gate to an effective equivalent inverter is introduced. The series–connected transistors in the NAND gate are converted to an equivalent transistor in a two step process. The model used in this conversion is the modified n–th power law which is appropriate for the state of the art logic gates. This model takes into account second order effects of submicron devices such as body effect and carrier velocity saturation. To show the validity of the technique, the calculated output waveform of the equivalent inverter is compared that of the NAND gate using HSPICE simulations (level 49).<\div>
نمایش نتایج ۱ تا ۵ از میان ۵ نتیجه