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۱An UWB LNA With Butterworth Filter in 0.18μm CMOS technology
نویسنده(ها):
اطلاعات انتشار: دوازدهمین کنفرانس دانشجویی مهندسی برق، سال
تعداد صفحات: ۵
in this paper, a 3GHz–10GHz Ultra wideband (UWB) Low Noise Amplifier (LNA) typology is proposed. The broadband matching and the flat gain are two important factors for the broadband circuits. Besides those factors, the minimal Noise Figure (NF), good linearity, and the lower power consumption are also desired.The common gate input stage configuration is used in the proposed LNA to achieve the broadband input matching. The flat gain of the LNA is achieved by the combination of the inductor peaking load and the shunt inductor insertion between the cascade stages of LNA. The LNA is designed in the standard 0.18μm CMOS technology. The input reflection coefficient S11 and output reflection coefficient S22 are less than –8dB and –10dB. It achieved maximum power gain 14.8dB and the minimum noise figure is 3.6dB and S12 less of –42dB . It consumes 14.8mW from a 1.8–V supply voltage<\div>

۲An Ultra High Gain CMOS Low Noise Amplifier With Current–Reused Technique
نویسنده(ها): ،
اطلاعات انتشار: سیزدهمین کنفرانس دانشجویی مهندسی برق ایران، سال
تعداد صفحات: ۴
This paper describes a CMOS LNA utilizing a current reuse technique for Bluetooth front–end receiver in a TSMC 0.18–μm process. The current reuse technique, the noise and gain performance is improved also, providing dual functions of impedance match and DC current sharing. A bias resistor of large value is placed between source and the body node to prevent body effect and reduce noise. The power gain and the minimal Noise Figure (NF) are two important factors for the circuits. Besides those factors, good linearity, and the lower power consumption are also desired. The LNA achieves a small signal gain of 22 dB. The LNA acquires an NF of 2.8 dB with an input return loss of – 28.6 dB and an output return loss of –17.5 dB. The LNA consumes 9.4 mW from a 1.8–V supply.<\div>

۳A 0.9V,2mW, 3 to 5 GHz CMOS LNA with Current Reuse Topology
نویسنده(ها): ، ،
اطلاعات انتشار: چهاردهمین کنفرانس دانشجویی مهندسی برق ایران، سال
تعداد صفحات: ۴
This paper present a new low voltage ultra low power 3 to 5 GHz UWB LNA utilizing a current reuse technique with a simple high pass filter input matching network is proposed . The noise, gain and power performance is improved using inter stage network.The broad band matching , the flat gain and the minimal Noise Figure (NF) are three important factors for the broadband circuits. The implemented 0.18–μm CMOS LNA achieve –8.6 dB input return loss . It performs a 14.1dB maximum gain and a 2.75dB NFmin. Total Power consumption is only 2mW from a 0.9v supply voltage.The power consumption figure of merit(FoM1) and the tuning–range figure of merit(FoM2) are optimal at 7.05dB\mw and 1498 (v.w)–1 , respectively.Compared with previously published UWB LNA, the proposed LNA has smallest supply voltage of 0.9v and ultra low power.<\div>

۴A 0.6V, 1.3mW CMOS LNA for WLAN Application
نویسنده(ها): ، ،
اطلاعات انتشار: چهاردهمین کنفرانس دانشجویی مهندسی برق ایران، سال
تعداد صفحات: ۴
A fully integrated low noise amplifier suitable for ultra–low voltage and ultra–low–power WLAN applications is designed and simulated in a standard 0.18μm CMOS technology. By employing the folded cascode, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 12 dB with a noise figure of 3.8 dB, while consuming only 1.3mW dc power with an ultra low supply voltage of 0.6 V.<\div>

۵An Ultra High Gain Low Power Folded cascode CMOS LNA at 1.5 GHz With the Gate Resistance Used for Input Matching
نویسنده(ها): ، ،
اطلاعات انتشار: چهاردهمین کنفرانس دانشجویی مهندسی برق ایران، سال
تعداد صفحات: ۴
Design and simulated results of a fully integrated 1.5–GHz CMOS low–noise amplifier (LNA) is presented. To design this LNA, the parasitic input resistance of a metal–oxide–semiconductor field–effect transistor (MOSFET) is converted to 50Ω by a simple L–C network, hence eliminating the need for source degeneration. The Major Problem in the LNAs with folded cascode architecture is low reverse isolation. In this paper this parameter is improved by adding a transistor.The power gain and the minimal Noise Figure (NF) are two important factors for the circuits. Besides those factors, good linearity, input impedance matching, low supply voltage and the lower power consumption are also desired. The LNA achieves a small signal gain of 22.5 dB. The LNA acquires an NF of 2.6 dB with an input return loss of –17.2 dB and an output return loss of –16 dB. The LNA consumes 5.7 mW from a 0.8V supply, the presented LNA achieves the best overall performance when compared with the most recently published LNAs.<\div>

۶An Ultra Low Voltage Ultra Low Power Folded Cascode CMOS LNA Using Forward Body Bias Technology for GPS application
اطلاعات انتشار: نوزدهمین کنفرانس مهندسی برق ایران، سال
تعداد صفحات: ۴
A fully integrated low noise amplifier suitable for ultra–low voltage and ultra–low–power GPS applications is designed and simulated in a standard 0.18μm CMOS technology. By employing the folded cascode and forward body bias technique, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 17.6 dB with a noise figure of 3 dB, while consuming only 960μW dc power with an ultra low supply voltage of 0.45 V. The power consumption figure of merit(FOM1) and the tuning–range figure of merit(FOM2) are optimal at 18.33 dB\mw and 8.8(v.mw)–1 , respectively.<\div>

۷Design of Low–Voltage Low–power Dual–Band LNA with Using DS Method to Improve Linearity
اطلاعات انتشار: بیستمین کنفرانس مهندسی برق ایران، سال
تعداد صفحات: ۴
In this paper a low–voltage low–power Concurrent Dual–Band Low Noise Amplifier (LNA) with linearity improvement technique is presented. By using advantageous of current reuse (CR) topology andforward body biasing (FBB) technique the proposed LNA can operate at a reduce supply voltage and powerconsumption. The liberalized LNA’s is achieved using auxiliary transistor and utilizing derivative superposition (DS) method. Using TSMC 0.18umprocess, the IIP3 is improved more than 50%, with the cost of decrease 2dB gain for each band. LNA is designed at 2.4GHz and 5.2GHz for IEEE802.11a\b\gapplication with 2.89mW power consumption and 0.7V supply voltage<\div>

۸Design of 0.5V, 450μW CMOS Current Reuse LNA With the Gate Resistance Used for Input Matching and Forward Body Bias Technique
اطلاعات انتشار: بیستمین کنفرانس مهندسی برق ایران، سال
تعداد صفحات: ۵
In this paper, design and simulation results of a fully integrated 5–GHz CMOS LNA is presented. To design this LNA, the parasitic input resistance of a MOSFET is converted to 50Ω by a simple L–C network, hence eliminating the need for source degeneration. As it is analytically shown, this is because the former methods enhance the gain of the LNA by a factor that is inversely proportional to MOSFET’s input resistance. By employing the current reuse and forward body bias technique, the proposed LNA can operate at reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 12.6 dB with a noise figure of 3.9 dB, while consuming only 450μW dc power with an ultra low supply voltage of 0.5V. The power consumption figure of merit (<\div>

۹A High Efficient Fully Integrated Passive CMOS Rectifier for Wirelessly Powered Devices
اطلاعات انتشار: بیستمین کنفرانس مهندسی برق ایران، سال
تعداد صفحات: ۶
A highly efficient fully integrated passive CMOS rectifier is proposed in this paper. Using four ultra low power and low voltage techniques consist of: Negative to Positive Half Wave Converter (NPHWC), bootstrapped technique, Dynamic Bulk Biasing Regulation (DBBR) and Ultra Low Power Diodes (ULPD) withproper leakage current compensation technique, this new topology is very high efficient in wide input voltage range of both high voltagesand low voltage advanced sub–micron applications simultaneously. Unlike the recently proposed rectifiers, in this new rectifier, for wide range of AC input signal amplitude the power and voltagetransmission efficiency are higher than 90%. New proposed rectifier is applicable for bio–implantable systems with high current demands.The new full–wave rectifier also simulated and optimized only for low voltage advanced sub–micron applications. In |Vin|=0.4V the voltageand power transmission efficiency are 70.3% and 68.3% respectively. These values in |Vin|=0.5V reach to 82% and 69%respectively. This rectifier designed and simulated in 0.18μm standard CMOS technology<\div>
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