اضافه کردن به علاقه‌مندی‌ها

محل انتشار

Majlesi Journal of Telecommunication Devices

اطلاعات انتشار

دوم،شماره۲، Jun ۲۰۱۳، سال

صفحات

۳ صفحه، از صفحه‌ی ۲۱۹ تا صفحه‌ی ۲۲۱

کلمات کلیدی

1، Simulation، performance، stability، In

In this paper a novel 1–bit full adder using hybrid–CMOS logic style is proposed. Hybrid–CMOS design style utilizes various CMOS logic style circuits to build new full adder with desired performance. The new proposed full adder is based on differential cascode voltage switch logic (DCVSL) XOR–XNOR gate which generate full–swing outputs. The complementary pass–transistor logic (CPL) is used to have minimum propagation delay and stability against noise in Sum signal. Also the transmission–gate logic (TG) is used to have high speed and full–swing in Cout signal. The circuit that consists of 16 transistors is simulated with HSPICE in 0.18 μm CMOS process by varying supply voltages from 1 V to 1.8 V with 0.2 V steps. The simulation results show that the proposed circuit has less power consumption and is faster in comparison to other circuits.

راهنمای دریافت مقاله‌ی «Design of Novel Hybrid–CMOS Full Adder with Low Power Consumption, High Speed and Full Swing Outputs» در حال تکمیل می‌باشد.

دریافت فایل PDF

۳۵۰۰۰ تومان

دریافت فایل Word + PDF

۱۱۰۰۰۰ تومان