Design Three Low Power, Low Delay CMOS 1–Bit Full Adder Cellپانزدهمین کنفرانس دانشجویی مهندسی برق ایران
1–bit full adder cell is a very great part in the design of application particular integrated circuits. Power consumption is one of the most significant parameters of full adders. Therefore reducing power consumption in full adders is very important in low power circuits. In this paper proposed three new structure of hybrid full adders, which we implemented by the Swing Restored Pass transistor Logic – Branch Based Logic, Differential Cascode Voltage Switch Logic – Differential Cascode Voltage Switch Pass Gate and Differential Pass Logic – Branch Based Logic . The proposed full adders called SRPL–BBL cell, DCVSL–DCVSPG cell and DPL–BBL cell. The Simulation results performed by HSPICE in TSMC 0.13 μm CMOS process. The results indicate the superiority the proposed full adders against several low power 1–bit full adder cells in terms of delay, power consumption, and power delay product.<\div>
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