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۱Design of 0.5V, 450μW CMOS Current Reuse LNA With the Gate Resistance Used for Input Matching and Forward Body Bias Technique
اطلاعات انتشار: بیستمین کنفرانس مهندسی برق ایران، سال
تعداد صفحات: ۵
In this paper, design and simulation results of a fully integrated 5–GHz CMOS LNA is presented. To design this LNA, the parasitic input resistance of a MOSFET is converted to 50Ω by a simple L–C network, hence eliminating the need for source degeneration. As it is analytically shown, this is because the former methods enhance the gain of the LNA by a factor that is inversely proportional to MOSFET’s input resistance. By employing the current reuse and forward body bias technique, the proposed LNA can operate at reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 12.6 dB with a noise figure of 3.9 dB, while consuming only 450μW dc power with an ultra low supply voltage of 0.5V. The power consumption figure of merit (<\div>

۲Design Three Low Power, Low Delay CMOS 1–Bit Full Adder Cell
اطلاعات انتشار: پانزدهمین کنفرانس دانشجویی مهندسی برق ایران، سال
تعداد صفحات: ۶
1–bit full adder cell is a very great part in the design of application particular integrated circuits. Power consumption is one of the most significant parameters of full adders. Therefore reducing power consumption in full adders is very important in low power circuits. In this paper proposed three new structure of hybrid full adders, which we implemented by the Swing Restored Pass transistor Logic – Branch Based Logic, Differential Cascode Voltage Switch Logic – Differential Cascode Voltage Switch Pass Gate and Differential Pass Logic – Branch Based Logic . The proposed full adders called SRPL–BBL cell, DCVSL–DCVSPG cell and DPL–BBL cell. The Simulation results performed by HSPICE in TSMC 0.13 μm CMOS process. The results indicate the superiority the proposed full adders against several low power 1–bit full adder cells in terms of delay, power consumption, and power delay product.<\div>

۳Design of 0.4 V operational amplifier using low–power techniques
اطلاعات انتشار: Majlesi Journal of Telecommunication Devices، دوم،شماره۱،Mar ۲۰۱۳، سال
تعداد صفحات: ۵
In this paper a low–power low–voltage CMOS operational amplifier (op amp) using sub–threshold region of MOSFET for bio–medical instrumentation operating with a 0.4 V supply is described. A two stage operational amplifier is designed and simulated using 0.18 μm CMOS technology. Two types of low–power low–voltage design techniques (a) bulk–driven (b) dynamic threshold voltage MOSFET (DTMOS) are used. With bulk–driven technique, the open loop gain is 69.88 dB, the unity gain–bandwidth (UGBW) is 87.1 kHz, CMRR obtained is 83 dB and phase margin is 88.78 degree with 10pF load. The power consumption is 1.8 μW. With DTMOS technique, the open loop gain is 83.31 dB, the unity gain–bandwidth is 758.6 kHz, CMRR obtained is 157.1 dB and phase margin is 71.5 degree with 10pF load. The power consumption is 1.8 μW. DTMOS technique provides high unity gain–bandwidth and high open loop gain as compared to bulk–driven technique.

۴A 0.4 V Low Frequency Voltage–Controlled Ring Oscillator Using DTMOS Technique
اطلاعات انتشار: Majlesi Journal of Telecommunication Devices، دوم،شماره۱،Mar ۲۰۱۳، سال
تعداد صفحات: ۵
In this paper, an ultra–low power ultra–low voltage five–stage low frequency voltage–controlled single–ended ring oscillator using dynamic threshold voltage MOSFET (DTMOS) is presented. The proposed oscillator is designed and simulated using TSMC 0.18μm RF CMOS technology with 0.4 V power supply. In this design all transistors working at the sub–threshold (weak inversion) region. The output frequency ranges from 26.6–210.5 kHz with control voltages of 0 V to 0.4 V. Its power consumption and phase noise at a 100 kHz offset at the minimum(maximum) oscillation frequency is respectively 6.42nW (8.62 nW) and –120.5 dBc\Hz (–113.15 dBc\Hz).

۵Overview of Low–Voltage Low–Power Design Techniques and Design Low–Voltage Low–Power Low–Noise Operational Amplifier
اطلاعات انتشار: Majlesi Journal of Telecommunication Devices، دوم،شماره۲، Jun ۲۰۱۳، سال
تعداد صفحات: ۷
In this paper an overview of circuit techniques dedicated to design low–power low–voltage is presented. These techniques (a) dynamic threshold voltage MOSFET (DTMOS) (b) bulk–driven and (c) current–driven bulk (CDB) are applied to design low–power low–voltage and low–noise CMOS operational amplifier (op amp) using sub–threshold region of MOSFET for bio–medical instrumentation operating with a 0.6 V supply. The operational amplifier is designed and simulated using TSMC 0.18μm CMOS technology. With DTMOS technique, the open loop gain is 60.51 dB, the unity gain–bandwidth (UGBW) is 12.08 kHz, phase margin is 52.3 degree and power consumption is 53.21 nW. With bulk–driven technique, the open loop gain is 49.04 dB, the unity gain–bandwidth is 3.32 kHz, phase margin is 71.96 degree and power consumption is 53.3 nW. With CDB technique, the open loop gain is 53.54 dB, the unity gain–bandwidth is 19 kHz, phase margin is 50 degree and power consumption is 55.79 nW. DTMOS technique provides high open loop gain, CDB technique provides high unity gain–bandwidth and bulk–driven technique provides better phase margin. Also DTMOS technique has less input–referred noise than the other methods.

۶Design of Novel Hybrid–CMOS Full Adder with Low Power Consumption, High Speed and Full Swing Outputs
اطلاعات انتشار: Majlesi Journal of Telecommunication Devices، دوم،شماره۲، Jun ۲۰۱۳، سال
تعداد صفحات: ۳
In this paper a novel 1–bit full adder using hybrid–CMOS logic style is proposed. Hybrid–CMOS design style utilizes various CMOS logic style circuits to build new full adder with desired performance. The new proposed full adder is based on differential cascode voltage switch logic (DCVSL) XOR–XNOR gate which generate full–swing outputs. The complementary pass–transistor logic (CPL) is used to have minimum propagation delay and stability against noise in Sum signal. Also the transmission–gate logic (TG) is used to have high speed and full–swing in Cout signal. The circuit that consists of 16 transistors is simulated with HSPICE in 0.18 μm CMOS process by varying supply voltages from 1 V to 1.8 V with 0.2 V steps. The simulation results show that the proposed circuit has less power consumption and is faster in comparison to other circuits.

۷Phase Noise Calculation in CMOS Single–Ended Ring Oscillators
اطلاعات انتشار: Majlesi Journal of Telecommunication Devices، دوم،شماره۳، Sep ۲۰۱۳، سال
تعداد صفحات: ۷
All oscillators are periodically time varyingsystems, so to accurate phase noise calculation andsimulation, time varying model should be considered. Phasenoise is an important characteristic of oscillator design anddefined as the spectral density of the oscillator spectrum atan offset from the center frequency of the oscillator relativeto the power of the oscillator. Linear time invariant (LTI) andlinear time variant (LTV) model’s for calculating phase noisein ring oscillator is discussed. In this paper a new techniquebased on LTV model for impulse sensitivity function (ISF)calculation and thus phase noise estimation inCMOS single–ended ring oscillator is presented. This methodis simpler than other methods and ISF can be simulated andcalculated easily. Good results between theory and simulationis observed.

۸Design of High Isolation Ka–band Radio Frequency MEMS Capacitive Shunt Switch
اطلاعات انتشار: Majlesi Journal of Telecommunication Devices، دوم،شماره۴، Dec ۲۰۱۳، سال
تعداد صفحات: ۶
Radio frequency (RF) micro electro–mechanical systems (MEMS) switches are rapidly replacing the PIN diodes and field–effect transistors (FET). Linear behavior, low power consumption, low insertion loss, high isolation, improvement power handling and etc. are benefits of MEMS switches. This paper presents a high isolation RF MEMS capacitive switch with two shunt beams for Ka–band (27–40 GHz) applications such as in communications satellites. Simulation results using Ansoft’s high frequency simulation software (HFSS) at Ka–band shows in the down–state of switch, the isolation (S21) is > 47 dB and return loss (S11) is 0.3 dB. In the up–state, the insertion loss (S21) is less than 0.15 dB and the return loss (S11) is more than 18 dB. The pull down voltage of designed switch is 5.13 V and down–state to up–state capacitance ratio (Cd\Cu=12.11pF\0.137pF) is 88.39. Also a novel index material (IM2) is proposed to determine optimum material using Ashby approach. In this paper the Aluminum (Al) is chosen for the membrane for having low pull down voltage and silicon nitride (Si3N4) is chosen for dielectric for having faster switching speed and larger down–state capacitance.
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